Basically the same thing amd is doing with their crazy high L3 cache cpus like the 5800x3d. Sounds like a good idea to apply the idea to GPU’s too.
No, not the same. AMD is using 2.5D, their cache sits next to the processor and any stacking stacks on top of the cache (something HBM has done for a long time)
Not necessarily gonna be as helpful on GPUs. We’ll see.
ELI5,
why the cache/memory always seems to be on top of the processing chip, not bottom?
Heat. The processor generates most of the heat, so you want the back side of the die somewhere a heat spreader can more or less directly connect to.
Well Top/Bottom is relative. But I assume you meant Top as in the side facing the heatsink.
Memory is “cooler” than dynamic logic, you want the colder element on top of the hotter one on the path of maximum dissipation.
Because power delivery throughout a CPU has been from top to bottom for decades (no idea why they went with this in the first place), Intel is working on inverting this and having power delivered from bottom to top and will see this realized in either their Arrowlake or later generation of Desktop CPU’s.
Potentially this inversion of power delivery will enable them to place the memory beneath everything and improve thermal characteristics.
These are all in flip-chip packages. So no, power would come up through the bottom, and the transistors would be closest to the top.
Given everything has been evolution from discrete valve tubes onwards, so there is a lot of it just being the easiest way to provide the connection to the rest of the system in a manner that you can hand off easily to the motherboard designers to be cheaply and efficiently mounted.
this could be a game changer if they can overcome the cooling and clock speed challenges, but the potential cost savings and production efficiency could make it worth it. excited to see where this goes!
Isn’t it Intel did this before?
Didn’t Intel’s CEO recently mention putting cache on top of compute was an aspiration of his? Seems to hint that they’re making this
No, Intel hasn’t talked about stacking HBM (or similar DRAM tech). They seem to be basically 3-4 years behind TSMC in hybrid bonding.
He’s made that statement a few times this year, even like a few weeks ago. Clearly a product is coming, we just dont know when or what.
So basically like AMD’s X3D
cool concept but i’m worried about the potential cooling challenges and manufacturing complexities. could be a game changer if they can overcome those hurdles though
this could be a game changer if they can overcome the cooling and clock speed challenges, but the potential cost savings and production efficiency could make it worth it. excited to see where this goes!
I think that wouldnt be cheap solution. Also the idea pehind scraped RDNA 4C and upcoming RDNA5 already show similar solution. Some leaks sugest the same for Zen 6.